This application claims the benefit of the Korean Application No. P2001-86764 filed in Korea on Dec. 28, 2001, which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same having a storage-on-gate system.
2. Discussion of the Related Art
As an information society develops, so does the demand for various types of displays. Recently, efforts have been made to research and develop various types of flat display panels, such as Liquid Crystal Display (LCD), Plasma Display Panel (PDP), Electroluminescent Display (ELD), Vacuum Fluorescent Display (VFD), and the like. An LCD is widely used as a substitution for a Cathode Ray Tube (CRT) because of the characteristics or advantages of a high quality image, light weight, shallow depth, compact size, and low power consumption. An LCD is applicable to devices that receive display signals, such as a television, computer monitor, and the like. Various technical developments for different types of LCD have been made such that LCDs play a role as an image display in various fields. However, in order for an LCD to be used as a general display device for a variety of various fields, the LCD needs to realize a high quality image with high resolution, a high brightness, a wide screen and the like, as well as, maintain the characteristics of light weight, shallow depth, compact size, and low power consumption
In general, a liquid crystal display includes two substrates in which electrodes on one substrate confront an electrode on the other substrate. A liquid crystal is injected between the confronting electrodes of the substrates. If a voltage is applied across the confronting electrodes, which generate an electric field, liquid crystals molecules are driven in accordance with the electric field and thus light transmittance through the substrates is varied. There are various types of liquid crystal displays. In particular, an Active Matrix Liquid Crystal Display (AM-LCD) contains thin film transistors that are respectively connected to pixel electrodes. The pixel electrodes, which are on one substrate, are arranged in a matrix and confront a common electrode, which is on the other substrate. The pixel electrodes and common electrode drive liquid crystal molecules by applying an electric field between the substrates in a direction vertical to the substrates. The AM-LCD provides excellent resolution for displaying moving images.
A liquid crystal display according to the related art is explained by referring to the attached drawings of FIG. 1 and FIG. 2. As shown in FIG. 1, a plurality of gate lines 11 is formed in one direction on a lower array substrate 10 of a liquid crystal display. A gate 12 protrudes from one side of each of the gate lines 11. A plurality of data lines 14 is formed perpendicularly to the gate lines 11 that cross over the gate lines 11. Pixel areas are defined between pairs of data lines and gate lines adjacent to where they cross over each other. Source electrodes 15 protrude from one side of each of the data lines 14. A drain electrode 16 is separated from the source electrode 15 by a predetermined interval. The drain electrode connects to a pixel electrode 18 through a contact hole 17a. Moreover, the source electrode 15, drain electrode 16, and gate electrode 12 are parts of a thin film transistor T.
FIG. 2 is a cross-sectional view along line II-IIxe2x80x2 in FIG. 1 showing that the thin film transistor includes an active layer 13xe2x80x2 of amorphous silicon over the gate electrode 12. A gate insulator 22 insulates amorphous silicon layer 13 from the gate electrode 12. The source electrode 15 and drain electrode 16 respectively overlap separate sides of the gate electrode 12. The amorphous silicon layer 13 includes a pair of ohmic contact layers 13xe2x80x3 that respectively connect the source electrode 15 and drain electrode 16 to the active layer 13xe2x80x2.
An upper electrode 19a, as shown in FIG. 1, is formed for a storage capacitor Cst that maintains a pixel voltage on the pixel electrode 18. The upper electrode 19a of the storage capacitor Cst is formed of an opaque metal layer having a predetermined pattern. The lower electrode of the storage capacitor Cst is the gate line 11b for an adjacent cell, as shown in FIG. 1. The upper electrode 19a is formed to overlap the gate line 11b when the data line 14 and/or source electrode 15 is formed. The upper electrode 19a is insulated from the gate line 11b by the gate insulator 22. Hence, the gate line 11b, upper electrode 19a and gate insulating layer 22 construct the storage capacitor Cst of a storage-on-gate system.
A passivation layer 24 is formed to cover the source electrode 15, drain electrode 16, the first semiconductor layer 13 and the upper electrode 19a. The passivation layer 24 can be formed of silicon oxide, silicon nitride or other types of insulating materials. A pixel electrode 18 made of a transparent conductive material, such as indium-tin-oxide, is formed in each of the pixel areas on the passivation layer 24 such that it overlaps the upper electrode 19a and the drain electrode 16 in part. A contact hole 17a is formed in the passivation layer 24 at a portion where the pixel electrode 18 and drain electrode 16 overlap each other. In addition, another contact hole 17b is formed in the passivation 24 to expose a predetermined portion of the upper electrode 19a, as shown in FIG. 2. The pixel electrode 18 connects to the drain electrode 16 and upper electrode 19a through the contact holes 17a and 17b, respectively.
The cross-sectional view shown in FIG. 2 illustrates a storage-on gate part A and a thin film transistor part B of a cell for explaining the method of making the related art device. Referring to FIG. 2, a gate line 11b of an adjacent cell is formed on a lower array substrate 10 in the storage-on-gate part A. A gate line 11a of the cell is formed on the lower substrate 10 in the thin film transistor part B. A gate electrode 12 extending from the gate line 11a of the cell is formed in the thin film transistor part B. A gate insulating layer 22 is formed on the gate lines 11a and 11b and over entire surface of both the storage-on-gate part A and thin film transistor part B. A semiconductor layer 13 is formed in a thin film transistor forming area on the gate insulating layer 22 of the thin film transistor part B. The first semiconductor layer 13 includes, for example, an active layer 13xe2x80x2 of amorphous silicon and a pair of ohmic contact layers 13xe2x80x3 of doped amorphous silicon on the active layer 13xe2x80x2. The doped semiconductor layers or ohmic contact layers 13xe2x80x3 are for ohmic contact and over-etch prevention. A source electrode 15 and a drain electrode 16 are formed to respectively overlap and connect to an ohmic contact layer 13xe2x80x3. In this case, the source electrode 15 is an electrode extending from the data line 14. In addition, an upper electrode 19a that overlaps an adjacent gate line 11b is formed in the storage electrode part A simultaneously when the source and drain electrodes 15 and 16 are formed. A passivation layer 24 is formed over the upper electrode 19a, source electrodes 15, drain electrodes 16 and the semiconductor layer 13. Contact holes 17a and 17b exposing predetermined portions of the drain electrode 16 and opaque metal layer 19a respectively are formed in the passivation layer 24. A pixel electrode 18 made of a transparent material is formed on the passivation layer 24 and connected to the drain electrode 16 and upper electrode 19a through contact holes 17a and 17b, respectively.
However, the fabrication of the above-constituted liquid crystal display has the following problems or disadvantages. Typically, the metal used for the source electrode and drain electrode is Molybdenum (Mo). The Mo does not have etch selectivity to the etchant of the passivation layer that overlies the thin film transistor and the storage-on-gate system. The ohmic contact layers on the active layer in the thin film transistor have etch selectivity to the etchant used in the etching of the passivation layer. Therefore, the etchant cannot etch through the ohmic contact layer into the active layer if the etchant etches through the Mo of the source and drain electrodes. In the capacitor structure of a storage-on-gate system using Mo as the upper electrode, when the contact hole is formed in the passivation layer above the upper electrode, the Mo does not have etch selectivity to the etchant of the passivation layer. Hence, the upper electrode of the storage-on-gate system can be etched. If the Mo is over-etched, the gate insulating layer between the upper electrode metal layer and the gate electrode of an adjacent cell can be removed or breached. Thus, a subsequently deposited pixel electrode can be short-circuited to the gate line of an adjacent cell if the gate insulating layer is removed or breached by the etchant. Such a short-circuit will prevent an LCD from operating properly.
Accordingly, the present invention is directed to a liquid crystal display device and a method of manufacturing the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same to provide a stable upper electrode connection structure.
Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same that maintain the integrity of a storage capacitor in a storage-on-gate system in the liquid crystal display device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a liquid crystal display device includes a substrate, first and second gate lines on the substrate, wherein each gate line has at least one gate electrode, a gate insulating layer above the gate lines, at least one data line crossing over the gate lines, a first semiconductor layer above a gate electrode of the first gate line, a source electrode connected to the data line and overlapping a first side of the first semiconductor layer, a drain electrode overlapping a second side of the first semiconductor layer, a second semiconductor layer adjacent to and above the second gate line, an upper electrode covering the second semiconductor layer and at least partially overlapping the second gate line, a passivation layer above the drain electrode and the upper electrode, contact holes in the passivation layer above the drain electrode and the second semiconductor layer and a pixel electrode on the passivation layer that is connected to the drain electrode and the upper electrode through the contact holes.
In another aspect of the present invention, a method of manufacturing a liquid crystal display device on a substrate includes the steps of forming first and second gate lines on the substrate, wherein each gate line has at least one gate electrode, forming a gate insulating layer above the gate lines, forming at least one data line crossing over the first and second gate lines, forming a first semiconductor layer above a gate electrode of the first gate line, forming a source electrode connected to the data line and overlapping a first side of the first semiconductor layer, forming a drain electrode overlapping a second side of the first semiconductor layer, forming a second semiconductor layer adjacent to the second gate line, forming an upper electrode covering the second semiconductor layer and at least partially overlapping the second gate line, forming a passivation layer above the drain electrode and the upper electrode, forming contact holes in the passivation layer above the drain electrode and the second semiconductor layer and forming a pixel electrode on the passivation layer that is connected to the drain electrode and the upper electrode through the contact holes.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.